Dr. John Heinlein, Vice President, Marketing, ARM Physical IP Division
 Mark Twain In 1897, after a journalist erroneously reported the passing of famed author and humorist Mark Twain, Twain replied in his typical wit with the now famous retort: “the rumor of my death has been greatly exaggerated.” Like the then very alive author, recent reports have speculated on the demise of the foundry and IP business model. I similarly think such talk is pure nonsense. Across many metrics the foundry and IP space is alive and well and providing unprecedented capabilities to semiconductor companies.
Let’s put the tabloid down and look at the facts from a few different perspectives. Continue reading “Foundry and IP Business Model: Alive and Well” »
Bill Rogers, Member Technical Staff, IPextreme
With growing support from debug/test hardware providers such as Goepel, Lauterbach, ASSET Intertech, and Corelis, and adoption by the Nexus 5001™ Forum, the IEEE 1149.7 standard has become firmly established as an enhancement to the ubiquitous IEEE 1149.1 standard. Continue reading “Ecosystem Growth Spurring IEEE 1149.7 Adoption in SoCs” »
Nikos Zervas, VP of Marketing, CAST, Inc.
The adoption of a reliable design reuse methodology, proliferation of high-quality IP products, and shake-out of the most untrustworthy IP vendors creates a situation offering a huge potential advantage to system integrators and product designers looking to jump ahead of their competition. Continue reading “Leapfrogging The Competition Through Smart IP Selection” »
Jack Browne, Sr. VP Sales & Marketing, Sonics, Inc.
As the fabless era disaggregated EDA and IP offerings, there are areas where in- house development is still the norm, even with today’s $2.5B IP industry. One of these is on-chip network – connecting the IP cores and memory subsystem.
On-chip interconnect or networks-on-chip (NoCs), in many companies, is still regarded as a part of the IP that can be internally developed for SoCs. With deeper process nodes, such as 28nm, enabling device convergence, more cores are included in the SoC, accelerated further by subsystems. Continue reading “Breaking Down the “Make vs. Buy” Barriers for IP” »
D. Christopher Keil, VP of Business Development, ChipStart LLC
The increasing momentum around adopting software-defined networking (SDN), which communications markets are currently experiencing, is accelerating the need for more comprehensive system management at the system-on-chip (SoC) level.
SDN introduces the notion of “random” events sequencing, such as changing the flow of a routing or switching path in real time from sources external to the network device. Random event change management, in turn, introduces new architectural challenges for communications SoCs because the state operation sequences to be executed are not predictable, as is the case when fully contained within the network device. Continue reading “New Software-Defined Networking Trend Changing the Way Silicon IP is Being Used” »
Ed Bard, Sr. Director of Marketing, Digital IP, Memories, Logic Libraries, FPGA Prototyping & Synthesis, Synopsys Inc.
This is obviously not a new subject; IP subsystems have existed for a very long time. They have been created by semiconductor companies and used and then reused in multiple projects. While this captive development exists, there is still no commercial IP subsystems market. It is inevitable, however, that successful commercial IP subsystems will emerge – for the same reasons that the current IP market exists:
- Shorter market windows
- Increased design complexity and costs
- Move to fab-lite
- Moore’s Law
Continue reading “Coming to a Theater Near You: The IP Subsystem” »
Kurt Wolf, Founder and President, Silicon-IP Inc.
System-on-chip (SoC) design companies contract experts in third-party intellectual property (IP) due diligence to support their internal IP management resources. Projects are typically scoped in one of two ways: (1) provide collaborative decision making in an IP field unfamiliar to SoC companies or (2) augment internal resources when the workload exceeds the steady state resource level. An SoC company obtains, on a rapid learning curve, the knowledge, insight and ranked recommendations for new IP companies and products to make final trade-off decisions based on their specific engineering and product requirement strategy. These expert advisors compliment the internal capabilities of SoC companies in the following ways: on-demand expertise, proprietary best practices and constant interaction with the IP ecosystem. These items are explained below. Continue reading “Outsourcing Third-Party IP Due Diligence” »
Warren Savage, CEO of IPextreme and Chairman of GSA’s IP Working Group
Occasionally, someone will get my dander up again on the topic of whether the IP business is a product business, a service business or both. The debate often gets a cute spin by people supporting the service point of view saying that certain IP can be “pre-made” and shrinkwrapped for sale, but other IP is baked on the customer site with some recipe tweaks by the customer.
Well…that’s a nice analogy, but let’s get real. If the final baking (aka verification) and recipe (feature set) needs to be done with the help of the customer, then that’s more design services than IP. I have no issues with design service companies, except for when they masquerade as IP companies. There is a real role for these companies in today’s semiconductor industry because there is a need for glue that holds together the real IP in the system. Use the same code once, that’s “IP.” Use it twice, that’s IP. Continue reading “Repeat After Me: IP is a Product Business” »
John A. Ford, Director of Product Marketing, Physical IP Division, ARM
On October 6th, UMC announced the selection of the ARM® Artisan® Physical IP Platform for the UMC foundry sponsored IP program. This new platform for UMC’s 28nm high-K metal gate (HKMG) process is a natural continuation of the long standing relationship between ARM physical IP division and UMC. ARM Artisan IP has been successfully used in millions of SoCs produced at UMC for more than 10 years on 180nm, 130nm, 90nm, 65nm and 55nm process technologies. The addition of UMC to ARM’s family of 28nm Physical IP platforms has a larger meaning than just a high quality set of IP on a technology-leading process. ARM Artisan IP is now the only physical IP platform available at all four of the 28nm commercial foundries in the world: TSMC, UMC, GLOBALFOUNDRIES, and Samsung. Continue reading “Clean Sweep at 28nm for ARM Artisan Physical IP” »
Brian Gardner, VP of Business Development, True Circuits, Inc.
You wouldn’t expect a guy from a hard IP company to be sounding a call about software. But, the cost of developing an SoC is projected by experts to exceed $50 billion in the future. Creating and validating the software required will become the largest portion. This rising cost threatens to change the semiconductor landscape, driving out all but the most wealthy semiconductor manufactures, and pushing the industry away from its entrepreneurial roots that created the PC, the cell phone, and the internet. Such a new world would be unkind to our EDA/IP business… so, software is our problem too.The need for this call to action became clear to me at Gary Smith’s presentation at this year’s DAC. Gary challenged the EDA/IP industry to do more to reduce the hardware cost of developing an SoC, while indicating that the software cost was not “our” problem. I believe we in the IP industry can do our part, and our future may depend on it. Continue reading “Software? The cost of developing an SoC is skyrocketing, and it’s the software” »
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